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/2/4, /4/5/6 CLOCK
GENERATION CHIP
ClockWorksTM SY100S839V FINAL
FEATURES
s s s s s s 3.3V and 5V power supply option 50ps output-to-output skew 50% duty cycle outputs Synchronous enable/disable Master Reset for synchronization Internal 75K input pull-down resistors
DESCRIPTION
The SY100S839V is a low skew /2/4, /4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL/LVECL or, if positive power supplies are used, PECL/LVPECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC-coupled into the device. If a singleended input is to be used, the VBB output should be connected to the /CLK input and bypassed to ground via a 0.01F capacitor. The VBB output is designed to act as the switching reference for the input of the S839V under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The common enable (/EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one S839V, the MR pin need not be exercised as the internal divider designs ensures synchronization between the /2/4, and the /4/5/6 outputs of a single device.
s Available in 20-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
VCC 20 Q0 19 Q0 18 Q1 17 Q1 16 Q2 15 Q2 14 Q3 13 Q3 12 VEE 11
TOP VIEW SOIC Z20-1
1 VCC
2 EN
3
4 CLK
5 CLK
6 VBB
7 MR
8 VCC
9
10
DIVSELb0
DIVSELb1
TRUTH TABLE
CLK Z ZZ X /EN L H X MR L L H Function Divide Hold Q0-3 Reset Q0-3
NOTE: Z = LOW-to-HIGH transition ZZ = HIGH-to-LOW transition
DIVSELa
PIN NAMES
Q0, Q1 OUTPUTS Divide by 2 Divide by 4 Pin CLK /EN Function Differential Clock Inputs Synchronous Enable Master Reset Reference Output Differential /2/4 Outputs Differential /4/5/6 Outputs Frequency Select Input
Rev.: A Amendment: /0
DIVSELa 0 1 DIVSELb1 0 0 1 1
DIVSELb0 0 1 0 1
Q2, Q3 OUTPUTS Divide by 4 Divide by 6 Divide by 5 Divide by 5
MR VBB Q0, Q1 Q2, Q3 DIVSEL
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Issue Date: May, 1999
Micrel
ClockWorksTM SY100S839V
DC ELECTRICAL CHARACTERISTICS(1)
VEE = VEE (min) to VEE (max); VCC = GND
TA = -40C Symbol IEE VBB IIH VOH VOL VOHA VOLA VIH VIL IIL Parameter Power Supply Current Output Reference Voltage Input High Current Output HIGH Voltage(2) Output LOW Voltage(2) Output HIGH Voltage(3) Output LOW Voltage(3) Input HIGH Voltage Input LOW Voltage Input LOW Current(4) Min.
-- -1.38 --
TA = 0C Min.
-- -1.38 -- -1025
TA = +25C Max.
95 -1.26 150 -880
TA = +85C Min.
-- -1.38 -- -1025
Typ.
50 -- --
Max.
95 -1.26 150 -880
Typ.
50 -- -- -955
Min.
-- -1.38 -- -1025
Typ.
50 -- -- -955
Max.
95 -1.26 150 -880
Typ.
54 -- -- -955
Max.
95 -1.26 150 -880
Unit mA V A mV mV mV mV mV mV A
-1085 -1005
-1830 -1695 -1555 -1810 -1705 -1620 -1810 -1705 -1620 -1810 -1705 -1620 -1095 -- -1165 -1810 0.5 -- -- -- -- -- -- -1555 -880 -1035 -- -1165 -- -- -- -- -- -- -1610 -880 -1035 -- -1165 -- -- -- -- -- -- -1610 -880 -1035 -- -1165 -- -- -- -- -- -- -1610 -880 -1475 --
-1475 -1810 -- 0.5
-1475 -1810 -- 0.5
-1475 -1810 -- 0.5
NOTE: 1. Parametric values specified at: -3.0V to -3.8V or -4.2V to -5.5V. 2. VIN = VIH(Max) or VIL(Min): Loading with 50 to -2.0V. 3. VIN = VIH(Min) or VIL(Max): Loading with 50 to -2.0V. 4. VIN = VIL(Min).
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Micrel
ClockWorksTM SY100S839V
AC ELECTRICAL CHARACTERISTICS(1)
VEE = VEE (min) to VEE (max); VCC = GND
TA = -40C Symbol fMAX tPLH tPHL Parameter Maximum Toggle Frequency Propagation Delay to Output CLK Output (Diff.) CLK Output (S.E.) MR Output Within-Device Skew(2) Q0 -- Q3 Part-to-Part tS tH VPP VCMR Set-up Time Hold Time Q0 -- Q3 (Diff.) /EN /CLK DIVSEL CLK /CLK /EN CLK DIVSEL CLK Range(4), (5) TA = 0C TA = +25C TA = +85C Unit MHz ps 725 675 600 -- -- 250 400 100 150 250 -1.6 -- CLK MR Q 500 700 280 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 925 975 900 50 200 -- -- -- -- -- -0.4 100 -- -- 550 725 675 600 -- -- 250 400 100 150 250 -1.7 -- 500 700 280 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 925 975 900 50 200 -- -- -- -- -- -0.4 100 -- -- 550 725 675 610 -- -- 250 400 100 150 250 -1.7 -- 500 700 280 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 925 975 910 50 200 -- -- -- -- -- -0.4 100 -- -- 550 725 675 630 -- -- 250 400 100 150 250 -1.7 -- 500 700 280 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 925 975 930 50 200 -- -- -- -- -- -0.4 100 -- -- 550 ps ps mV V ps ps ps ps Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 1000 -- -- 1000 -- -- 1000 -- -- 1000 -- --
tskew
Minimum Input Swing(3) Common Mode
tRR
tPW tr
Reset Recovery Time Minimum Pulse Width Output Rise/Fall Times (20% --80%)
tf
NOTES: 1. Parametric values specified at: -3.0V to -3.8V or -4.2V to -5.5V. 2. Skew is measured between outputs under identical transitions. 3. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV. 4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP min. and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = -3.3V. Note for PECL operation, the VCMR (min) will be fixed at 3.3V - IVCMR (min)I. 5. Duty Cycle: (Min. 48%; Max. 52%) } over temp.
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Micrel
ClockWorksTM SY100S839V
LOGIC DIAGRAM
DIVSELa (/ 2/4) CLK CLK R
Q0 Q0 Q1 Q1
EN
(/4/5/6)
Q2 Q2 Q3
VBB
R
MR DIVSELb0 DIVSELb1
Q3
TIMING DIAGRAMS
CLK
Q (/ 2)
Q (/ 4)
Q (/ 5)
Q (/ 6)
PRODUCT ORDERING CODE
Ordering Code SY100S839VZC SY100S839VZCTR Package Type Z20-1 Z20-1 Operating Range Commercial Commercial
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Micrel
ClockWorksTM SY100S839V
20 LEAD SOIC .300" WIDE (Z20-1)
Rev. 03
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
FAX
+ 1 (408) 980-9191
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated
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